Research

RTL Testing & Verification

Hardware verification remains one of the most critical and time-consuming steps in chip design, which faces severe state and path explosion challenges in modern complex RTL designs. We integrate Large Language Models, intelligent agent, and warm starting state reuse to guide symbolic execution and scale model checking.

Our COTIA framework combines dynamic beam path search with LLM-based global exploration to break out of local optima in concolic testing. In parallel, Hot-FV accelerates formal verification by selecting contribution-aware starting states to bypass reset paths, cutting verification time in half while drastically lowering peak memory overhead.

• COTIA: agent-based framework to dynamically adjust path exploration strategies by leveraging beam search and large language models
• Hot-FV: Warm-started semi-formal model checking
• Fine-tuned LLMs for dynamic path exploration in RTL

RTL-level Microprocessor Fuzzing

Hardware verification requires exploring vast microarchitectural state spaces that traditional random instruction generators cannot efficiently cover. To address distinct bottlenecks in CPU simulation and RTL bug discovery, we have developed three fuzzing frameworks: SnapFuzz, FineGrainedFuzz, and STSearch.

SnapFuzz introduces fast RTL snapshotting and a two-level trap handler, enabling continuous exception-path testing without costly simulation resets. FineGrainedFuzz performs dependency-aware control-flow analysis to guide test generation directly toward complex microarchitectural dependencies. STSearch provides an automated search strategy specifically designed to navigate deep structural and temporal execution paths in hardware designs.

Together, these frameworks significantly accelerate microprocessor verfication speed, optimize coverage across complex modules, and have uncovered multiple new, verified bugs in open-source RISC-V processors including Rocket, BOOM, and XiangShan.

• SnapFuzz: Trigger hardware exceptions and employing an embedded handler to simulate the operating system’s trap-handling response
• FineGrainedFuzz: Dependency-aware control-flow analysis for fine-grained RTL guidance
• STSearch: Targeted state-space search for complex structural and temporal execution paths

LLM-Guided RTL Generation

We build automated frameworks to generate functional Hardware Description Languages (HDLs) directly from high-level specifications. Our research focuses on advancing Large Language Models (LLMs) for Verilog synthesis, emphasizing automated error correction, and functional verification.

A major bottleneck in AI-assisted chip design is that LLM-generated Verilog frequently suffers from subtle syntax and functional bugs. To address this, we developed AutoVeriFix—a closed-loop repair framework that leverages Python golden oracles to automatically detect and fix functional errors in generated RTL. Additionally, we introduced ChipVerilog, a large-scale, open-source benchmark constructed from hierarchical OpenCores IPs, establishing a rigorous standard for evaluating LLM capabilities in hardware design.

• LLM-guided Verilog RTL generation and benchmarking
• Closed-loop automated bug detection and repair using golden reference models

Hardware/Software Co-design

Achieving peak energy efficiency and throughput in domain-specific workloads—such as Deep Neural Networks (DNNs) and edge AI—requires simultaneous optimization across algorithms, custom hardware extensions, and microarchitectural design spaces. We develop multi-level co-optimization frameworks and automated exploration techniques to seamlessly bridge software requirements with target hardware platforms.

Our research spans model quantization, instruction set design, mapping optimization, and design space search:

• MiCo (Mixed-Precision Co-Exploration): A joint hardware/software co-design framework that optimizes mixed-precision neural network quantization alongside hardware accelerator resource allocation.
• BNRV (BitNet Acceleration on RISC-V): Custom RISC-V ISA extensions and specialized execution units designed to accelerate ultra-low-bit BitNet LLM architectures efficiently on edge processors.
• MACO (Hardware-Mapping Co-Optimization): A unified framework that simultaneously optimizes DNN accelerator spatial hardware topology and dataflow scheduling maps to maximize throughput and energy efficiency.
• SPaDE (Design Space Exploration via Space Partitioning): An automated microarchitectural exploration strategy that partitions massive hardware parameter spaces to rapidly identify Pareto-optimal processor configurations.
• Physics-Informed SRAM Exploration: Physics-informed modeling techniques that accelerate SRAM circuit-level design space exploration, bridging physical circuit constraints with high-level architectural optimization.

Machine Learning for PPA Modeling

Accelerating integrated circuit design and physical optimization requires moving beyond computationally prohibitive synthesis, layout, and characterization loops. We develop machine learning-based surrogate frameworks for power, performance, and area (PPA) prediction and rapid design space exploration (DSE) across microarchitectural cores and memory systems.

Our research spans physics-informed surrogate modeling, multi-corner Transformer architectures, and cycle-accurate dynamic power estimation:

• Accelerating SRAM DSE via Physics-Informed Models: A surrogate modeling framework combining domain-specific features with transfer learning to streamline multi-objective SRAM macro selection across advanced technology nodes.
• TransPPA (Transformer-Based Multi-Corner PPA Modeling): A unified deep learning architecture that predicts post-layout power, worst negative slack (WNS), and area across multi-corner PVT variations for RISC-V microprocessors.
• CPP-SGS (Cycle-Accurate Power Prediction): A fast, high-resolution power estimation model leveraging Spiking Neural Networks (SNNs) and genetic signal selection to track dynamic activity.

Differential Simulator Fuzzing

RTL simulators are not bug-free. We develop GI-RTL-Fuzz, a grammar-informed, LLM-guided fuzzing framework that systematically discovers semantic inconsistencies across multiple open-source and commercial simulators, including Verilator and Icarus Verilog.

By leveraging an ANTLR4 grammar analyzer, the framework identifies rare grammar constructs as generation targets, then prompts an LLM to synthesize syntactically valid but semantically corner-case RTL programs. A differential testing engine cross-checks outputs across simulators, and an agentic bug reporter classifies and documents discrepancies into actionable bug reports with IEEE 1800 references. We have reported 15+ previously unknown bugs to the Verilator and Icarus teams, with pull requests accepted to fix parser and semantic analysis issues.

• Grammar-informed LLM generation for differential simulator testing
• Automated bug classification and reporting against IEEE 1800
• Discovered 15+ previously unknown bugs in Verilator and Icarus Verilog
• Contributed pull requests to upstream simulator projects